DocumentCode :
3363926
Title :
A Capacitor Mismatch- and Nonlinearity-Insensitive 1.5-bit Residue Stage for Pipelined ADCs
Author :
Saberi, Morteza ; Lotfi, Reza
Author_Institution :
Ferdowsi Univ. of Mashhad, Mashhad
fYear :
2007
fDate :
11-14 Dec. 2007
Firstpage :
677
Lastpage :
680
Abstract :
In this paper, a novel structure for 1.5-bit residue stages, for use in pipelined ADCs, is proposed where the stage transfer characteristic is almost insensitive to neither the mismatches nor the non-linearities of capacitors. The proposed structure working in three phases is based on putting charged capacitors in series in the opamp feedback loop. Circuit simulations in 0.18 mum standard digital CMOS technology confirm the effectiveness of the proposed configuration.
Keywords :
CMOS integrated circuits; analogue-digital conversion; capacitors; circuit simulation; operational amplifiers; pipeline arithmetic; capacitor mismatch; charged capacitors; circuit simulations; digital CMOS technology; nonlinearity-insensitive residue stage; opamp feedback loop; pipelined ADC; stage transfer characteristic; Capacitors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location :
Marrakech
Print_ISBN :
978-1-4244-1377-5
Electronic_ISBN :
978-1-4244-1378-2
Type :
conf
DOI :
10.1109/ICECS.2007.4511082
Filename :
4511082
Link To Document :
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