A Capacitor Mismatch- and Nonlinearity-Insensitive 1.5-bit Residue Stage for Pipelined ADCs

In this paper, a novel structure for 1.5-bit residue stages, for use in pipelined ADCs, is proposed where the stage transfer characteristic is almost insensitive to neither the mismatches nor the non-linearities of capacitors. The proposed structure working in three phases is based on putting charged capacitors in series in the opamp feedback loop. Circuit simulations in 0.18 mum standard digital CMOS technology confirm the effectiveness of the proposed configuration.