Low-Leakage ROM Architecture for High-Speed Mobile Applications

Optimizing leakage currents in embedded memories is a major challenge, especially for portable applications. Increasing Vt of concerned memory transistors may not be the solution when target applications are also requiring high working frequencies. We describe in this paper a proven ROM architecture that reduces significantly leakage, without speed penalty. A dedicated testchip using a 0.18 mum CMOS Logic technology has been successfully designed and fabricated. On silicon stand-by current and speed measurements, performed on ROM configurations using both conventional and proposed architectures, confirmed our expectations.