DocumentCode
3364096
Title
Cell BE SOC Debug Features
Author
Riley, Mack ; Genden, Mike
fYear
2007
fDate
May 30 2007-June 1 2007
Firstpage
1
Lastpage
5
Abstract
The Cell BE processor incorporates a 64-bit Power Architecture processor coupled with eight Synergistic processors, a Flexible IO interface, and a memory interface controller that are all connected by a high speed element interconnect mechanism. The processor also supports multiple operating systems, including Linux. The challenge of bringing new architectures that operate at multi-Gigahertz functional and test speeds required additional attention to debug functions on the chip. This paper will explore some of the debug features that were added to the Cell BE design.
Keywords
microprocessor chips; system-on-chip; 64-bit Power Architecture processor; SOC; cell BE processor; cell broadband engine; debug features; flexible IO interface; high speed element interconnect mechanism; memory interface controller; system-on-chip; Clocks; Hardware; Level control; Microwave integrated circuits; Phase locked loops; Power system interconnection; Process design; Registers; System-on-a-chip; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuit Design and Technology, 2007. ICICDT '07. IEEE International Conference on
Conference_Location
Austin, TX
Print_ISBN
1-4244-0757-5
Electronic_ISBN
1-4244-0757-5
Type
conf
DOI
10.1109/ICICDT.2007.4299586
Filename
4299586
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