Dual Mode K-Best MIMO Detector Architecture and VLSI Implementation

Author

Shariat-Yazdi, Ramin ; Kwasniewski, Tadeusz

Author_Institution

Carleton Univ., Ottawa

fYear

2007

fDate

11-14 Dec. 2007

Firstpage

735

Lastpage

738

Abstract

Maximum likelihood (ML) detector is the optimal detector for multiple-input multiple-output (MIMO) communication systems. K-best decoding algorithm can achieve sub-optimal ML performance with reduced complexity. In this paper we present a novel dual mode architecture for implementation of K-best algorithm. The proposed architecture is fully parallel and can support both QPSK and 16-QAM modulation schemes. Implementation results show that detector´s throughput can reach 480 Mbps.

Keywords

MIMO communication; VLSI; decoding; maximum likelihood detection; quadrature amplitude modulation; quadrature phase shift keying; K-best decoding algorithm; MIMO communication systems; QAM modulation schemes; QPSK; VLSI implementation; dual mode MIMO detector architecture; maximum likelihood detector; multiple-input multiple-output communication systems; Detectors; Hardware; MIMO; Maximum likelihood decoding; Maximum likelihood detection; Radio transmitters; Signal processing algorithms; Throughput; Transmitting antennas; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on

Conference_Location

Marrakech

Print_ISBN

978-1-4244-1377-5

Electronic_ISBN

978-1-4244-1378-2

Type

conf

DOI

10.1109/ICECS.2007.4511096

Filename

4511096