DocumentCode :
3364278
Title :
Thermal cycling reliability assessment and enhancement of embedded wafer level LGA packages for power applications
Author :
Yiyi Ma ; Kim-Yong Goh ; Xueren Zhang ; Yonggang Jin
Author_Institution :
STMicroelectron., Singapore, Singapore
fYear :
2013
fDate :
11-13 Dec. 2013
Firstpage :
606
Lastpage :
611
Abstract :
With great feasibility and flexibility for growing I/Os, multi-chips and system integration, the emerging fan-out embedded Wafer Level BGA (eWLB) technology is regarded as a much more favorable packaging solution compared with its traditional counterparts, i.e. fan-in WLP or BGA technology. The relentless trend of ever increasing integrated circuit chip functionality and decreasing chip dimensions for miniaturization of products have led to less chip real estate and intense heat dissipation. While eWLB technology has well addressed the routing problems associated with the former, its intrinsic ineffectiveness of reducing the spreading thermal resistance of the shrunk die has limited its application to low power devices. As a result, Quad Flat No-Lead (QFN) is often a packaging technology of choice for those applications as QFN is a lead frame based package which offers thermal and electrical enhancement with its exposed die pad on the bottom of the package surface. The exposed die pad not only provides an efficient heat path to the PCB, but also enables stable grounding with electrical connection through a conductive die attach material. To bridge the gap between the eWLB and QFN concept so that both of their advantages can be retained, STMicroelectronics has recently come up with a QFN-like eWLB package known as embedded wafer level LGA (eWLL) with low profile, high pin count and excellent thermal and electrical performance. This paper initially investigated the solder joint reliability of the eWLL packages under board level Accelerated Thermal Cycling (ATC) test through Finite Element Analysis (FEA). Experiments were then carried out to assess the accuracy of the FEA model. It was found that the predictions made by the FEA simulation correlated very well with the actual test results. The validated FEA model was then extended to study the effect of a wide range of design variables on the board level reliability of the eWLL packages. The results of the numerical an- lysis are compared and discussed in details.
Keywords :
ball grid arrays; cooling; finite element analysis; life testing; microassembling; printed circuits; thermal resistance; wafer level packaging; FEA; I/O; PCB; STMicroelectronics; accelerated thermal cycling test; ball grid arrays; die attach material; die pad; electrical connection; electrical enhancement; embedded wafer level LGA packages; finite element analysis; grounding; heat dissipation; integrated circuit chip; lead frame based package; low power devices; multichips; numerical analysis; quad flat no-lead; solder joint reliability; system integration; thermal cycling reliability assessment; thermal enhancement; thermal resistance; Electronic packaging thermal management; Finite element analysis; Heating; Packaging; Reliability; Soldering;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference (EPTC 2013), 2013 IEEE 15th
Conference_Location :
Singapore
Print_ISBN :
978-1-4799-2832-3
Type :
conf
DOI :
10.1109/EPTC.2013.6745792
Filename :
6745792
Link To Document :
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