An unified approach for convolution-based image filtering on reconfigurable systems

Currently the market and the academic community have required applications of image and video processing with several real-time constraints. In order to seek an alternative design that allows the rapid development of real time image processing systems this paper proposes an unified hardware architecture for some image filtering algorithms in space domain, such as windowing-based operations, which are implemented on FPGAs (Field Programmable Gate Arrays). For achieving this, six different filters have been implemented in a parallel approach, separating them in simple hardware structures, allowing the algorithms to explore their parallel capabilities by using a simple systolic architecture. In this system all implemented algorithms run in parallel allowing the user to select a defined output for depicting it in a display. Both image processing and synthesis results have demonstrated the feasibility of FPGAs for implementing the proposed filtering algorithms in a full parallel approach.