High-performance memory interface architecture for high-definition video coding application

This paper proposes new memory interface architecture to overcome huge SDRAM bandwidth requirements of video decoders. To improve the memory efficiency, tile based memory access method and pixel cache are adopted. In addition to large data transfer cycle, extra overhead cycles takes great part of the heavy memory bandwidth requirement. The overhead cycles are caused by two reasons- the one is due to row-activation overhead of SDRAM and the other is due to redundant data transfer for motion compensation. The row-activation overhead is incurred frequently because of the block by block memory access pattern of standard video decoding algorithms. By using the tile based memory access method, the row-activation overhead can be reduced significantly. The redundant data transfer overhead is due to the 6-tap FIR filtering for the motion compensation while H.264/AVC decoding. We reduced the redundant memory transfer overhead by adopting the reference pixel cache, which is tightly coupled with multi-frame reference picture and the memory structure of the tile based memory access method. Experimental results show that the proposed method can decode 1920 × 1080, 30 frame per second H.264/AVC main profile bitstream in real time with only about 90MHz SDRAM clock. Compared to the conventional linear memory access system, the proposed method reduces about 6 times of SDRAM bandwidth. We also expect the proposed method will reduce power consumption because the SDRAM bandwidth requirement and the number of row-activation overhead are significantly reduced.