DocumentCode :
3364551
Title :
Balanced bipartitioning of a multi-weighted hypergraph for heterogeneous FPGAS
Author :
Mukhopadhyay, Sagnik ; Banerjee, Pritha ; Sur-Kolay, Susmita
Author_Institution :
Tata Inst. of Fundamental Res., Mumbai, India
fYear :
2011
fDate :
13-15 April 2011
Firstpage :
91
Lastpage :
96
Abstract :
In this paper, we present a heuristic algorithm for bipartitioning a netlist of modules having m types of heterogeneous resources, as in modern FPGAs with configurable logic blocks (CLBs), Block RAMs and Multipliers (MULs). The desired min-cut bipartition has to satisfy m constraints arising from given balance ratios, one for each type of resource. The netlist is represented as a hypergraph, whose vertices correspond to the modules. Each vertex has a m-tuple weight vector, denoting the number of resource units of each type. Our proposed multi-constraint bipartitioner is based on dynamic programming, which employs a single-constraint bipartitioner. The upper bounds for mean deviation in combined balance ratio, and for the increment in cut-size are presented. Experimental results on a set of benchmarks show that on the average there is negligible deviation in cut-size for multi-constraint bipartitions from single-constraint bipartion, while satisfying the individual balance ratio constraints for each type of resource.
Keywords :
dynamic programming; field programmable gate arrays; heuristic programming; balanced bipartitioning; block RAM; configurable logic blocks; dynamic programming; heterogeneous FPGA; heuristic algorithm; multipliers; multiweighted hypergraph; single-constraint bipartitioner; Complexity theory; Dynamic programming; Field programmable gate arrays; Frequency modulation; Logic gates; Partitioning algorithms; Upper bound;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Programmable Logic (SPL), 2011 VII Southern Conference on
Conference_Location :
Cordoba
Print_ISBN :
978-1-4244-8847-6
Type :
conf
DOI :
10.1109/SPL.2011.5782631
Filename :
5782631
Link To Document :
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