Title :
An ADPLL circuit using a DDPS for genlock applications
Author :
Calbaza, Dorin Emil ; Cordos, Ioan ; Seth-Smith, Nigel ; Savaria, Yvon
Author_Institution :
Gennum Corp., Burlington, Ont., Canada
Abstract :
This paper presents a fully programmable All-Digital PLL (ADPLL) circuit that is able to synchronize any frequency between 12 MHz and 200 MHz, with a frequency between 24 Hz and 100 MHz. This ADPLL circuit uses a Direct Digital Period Synthesizer as a digitally controlled oscillator. The measured jitter at the output is between 184 and 274 ps (depending on control parameters). The circuit is implemented in 0.18 μm CMOS technology and dissipates 50 mW when running at 150 MHz.
Keywords :
CMOS integrated circuits; crystal oscillators; digital phase locked loops; direct digital synthesis; synchronisation; timing jitter; 0.18 micron; 12 to 200 MHz; 50 mW; CMOS technology; digitally controlled oscillator; direct digital period synthesizer; genlock applications; jitter; programmable all digital PLL circuit; synchronization; CMOS technology; Circuits; Clocks; Frequency synchronization; Jitter; Oscillators; Phase frequency detector; Phase locked loops; Signal generators; Timing;
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
DOI :
10.1109/ISCAS.2004.1329067
