• DocumentCode
    3364748
  • Title

    TSV reveal process developments for 2.5D integration

  • Author

    Chongshen Song ; Lei Wang ; Zhun Wang ; Daquan Yu ; Wenqi Zhang

  • Author_Institution
    Nat. Center for Adv. Packaging (NCAP China), Wuxi, China
  • fYear
    2013
  • fDate
    11-13 Dec. 2013
  • Firstpage
    714
  • Lastpage
    717
  • Abstract
    2.5D integration using TSV silicon interposer has attracted much attention in recent years for both front-end foundries and back-end packaging houses. TSV back revealing is one of the key process modules for the fabrication of 2.5D interposer. Two kinds of process flows for TSV revealing are introduced and compared in this paper. The first one uses Si-Cu co-polishing for copper revealing, which can compensate the total thickness variation (TTV) of TSV tips, but the passivation opening on the back side of the TSVs becomes more and more difficult when the TSV size is scaling down. The second one reopens the backside of the TSVs after backside polymer passivation by mask-free plasma etching, which is advantageous for small TSVs but needs to control the TTV strictly. Fabrication results using these two process flows are given and discussed.
  • Keywords
    copper alloys; integrated circuit packaging; passivation; polishing; polymers; silicon alloys; sputter etching; three-dimensional integrated circuits; 2.5D integration; 2.5D interposer fabrication; Si-Cu; TSV reveal process developments; TSV silicon interposer; back-end packaging houses; backside polymer passivation; copolishing; copper revealing; front-end foundry; mask-free plasma etching; Copper; Dielectrics; Fabrication; Passivation; Polymers; Silicon; Through-silicon vias;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging Technology Conference (EPTC 2013), 2013 IEEE 15th
  • Conference_Location
    Singapore
  • Print_ISBN
    978-1-4799-2832-3
  • Type

    conf

  • DOI
    10.1109/EPTC.2013.6745813
  • Filename
    6745813