Chip on board (COB) versus board on chip (BOC) memory packages

Due to intense competition in the consumer electronics landscape, especially in the mobile communication products sector, new memory products (both DRAM and NAND Flash) must meet higher speed requirements, be packaged in smaller form factors, and achieve higher densities. Therefore, the most common package types-board on chip (BOC) for DRAM and chip on board (COB) for NAND Flash-must be analyzed to determine whether they can meet current and future packaging challenges. The components of COB and BOC substrates that are being studied are traces, bond fingers, the number of metal layers, and vias. Based on the trends of these substrate components, future substrates will be required to have at least two metal layers (BOC in particular), utilize narrower bond finger pitches, be thinner than 0.13mm and have vias with via land/drill hole sizes of less than 220μm/100μm. Further work must be performed to determine the minimum required trace width value based on the existing warpage specifications as well as the minimum required bond finger pitch as a function of die length.