• DocumentCode
    336490
  • Title

    On path delay fault testing of multiplexer-based shifters

  • Author

    Vergos, H.T. ; Tsiatouhas, Y. ; Haniotakis, Th ; Nikolos, D. ; Nicolaidis, M.

  • Author_Institution
    Dept. of Comput. Eng. & Inf., Patras Univ., Greece
  • fYear
    1999
  • fDate
    4-6 Mar 1999
  • Firstpage
    20
  • Lastpage
    23
  • Abstract
    In this paper we present a method for path delay fault testing of multiplexer-based shifters. We show that many paths of the shifter are non-robustly testable and we give a path selection method so as all the selected paths to be robustly testable by 20*log2n+2 test-vector pairs, where n is the length of the shifter. The propagation delay along all other paths is a function of the delays along the selected paths
  • Keywords
    VLSI; delays; digital integrated circuits; integrated circuit testing; integrated logic circuits; logic testing; multiplexer-based shifters; nonrobustly testable paths; path delay fault testing; path selection method; propagation delay; test-vector pairs; Circuit faults; Circuit optimization; Circuit testing; Delay effects; Manufacturing processes; Multiplexing; Propagation delay; Reliability engineering; Timing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
  • Conference_Location
    Ypsilanti, MI
  • ISSN
    1066-1395
  • Print_ISBN
    0-7695-0104-4
  • Type

    conf

  • DOI
    10.1109/GLSV.1999.757368
  • Filename
    757368
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=336490