• DocumentCode
    336494
  • Title

    ICE: incremental 3-dimensional capacitance and resistance extraction for an iterative design environment

  • Author

    Yuan, Yanhong ; Banerjee, Prithviraj

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
  • fYear
    1999
  • fDate
    4-6 Mar 1999
  • Firstpage
    64
  • Lastpage
    67
  • Abstract
    In this paper we discuss the 3-Dimensional (3-D) capacitance and resistance extraction within an iterative design environment, where small changes are made to the 3-D structures. We present a bounded incremental algorithm for accurate and fast 3-D extraction in such a design environment, based on the Boundary Element Method (BEM). The incremental algorithm can re-utilize the computation results of previous extractions and rapidly re-compute the new parasitic parameters in response to the design changes made to the layout. The incremental algorithm has been implemented in the ICE tool. Experimental results on a set of 3-D interconnect structures show that the incremental algorithm is efficient for the iterative design methodology. For one large structure, the incremental extraction is over 20 times faster than the full extraction without using the incremental algorithm. To the best of our knowledge, this is the first reported work on an incremental algorithm for capacitance and resistance extraction
  • Keywords
    VLSI; boundary-elements methods; capacitance; circuit layout CAD; electric resistance; integrated circuit interconnections; integrated circuit layout; iterative methods; 3D interconnect structures; BEM; IC layout; ICE tool; VLSI design; boundary element method; bounded incremental algorithm; incremental 3-dimensional extraction; incremental 3D capacitance extraction; incremental 3D resistance extraction; iterative design environment; parasitic parameters; three-dimensional structures; Algorithm design and analysis; Electric resistance; Ice; Integrated circuit interconnections; Iterative algorithms; Iterative methods; Parasitic capacitance; Pattern matching; Timing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
  • Conference_Location
    Ypsilanti, MI
  • ISSN
    1066-1395
  • Print_ISBN
    0-7695-0104-4
  • Type

    conf

  • DOI
    10.1109/GLSV.1999.757378
  • Filename
    757378