Study on dynamic modeling and reliability analysis of wafer thinning process for TSV wafer

Through-silicon-via (TSV) technology permits devices to be placed and wired in the third dimension. Currently, there is a strong motivation for the semiconductor industry to move to 3D integration using the TSV approach due to many advantages of TSV application. However, there are also some challenges for TSV processes. One of the challenges is TSV wafer thinning process. In this paper, a dynamic finite element modeling methodology was established and used to investigate the TSV process induced wafer stress. It was found that wafer surface roughness, TSV wafer thickness, bonding/debonding material, TSV feature size have impact on TSV wafer stress under the TSV wafer thinning process.