DocumentCode
336498
Title
Pseudo-exhaustive testing of sequential circuits
Author
Shaer, Bassam ; Al-Arian, Sami A. ; Landis, David
Author_Institution
Dept. of Electr. & Comput. Eng., Minnesota Univ., MN, USA
fYear
1999
fDate
4-6 Mar 1999
Firstpage
109
Lastpage
112
Abstract
A new sequential circuit partitioning algorithm is introduced which enhances pseudo-exhaustive testing. Our PIFAN algorithm is based on an analysis of Primary Input cones and FANout values. Results are presented which show that PIFAN offers significant reductions in hardware overhead and test time when compared to alternative partitioning algorithms
Keywords
VLSI; automatic testing; integrated circuit testing; integrated logic circuits; logic partitioning; logic testing; sequential circuits; PIFAN algorithm; circuit partitioning algorithm; fanout values; hardware overhead reduction; primary input cones; pseudo-exhaustive testing; sequential circuits; test time reduction; Algorithm design and analysis; Automatic testing; Circuit testing; Costs; Design engineering; Design for testability; Logic testing; Sequential analysis; Sequential circuits; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
Conference_Location
Ypsilanti, MI
ISSN
1066-1395
Print_ISBN
0-7695-0104-4
Type
conf
DOI
10.1109/GLSV.1999.757388
Filename
757388
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