Noise immunity of digital circuits in mixed-signal smart power systems

Author

Secareanu, Radu M. ; Kourtev, Ivan S. ; Becerra, Juan ; Watrobski, Thomas E. ; Morton, Christopher ; Staub, William ; Tellier, Thomas ; Friedman, Eby G.

Author_Institution

Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA

fYear

1999

fDate

4-6 Mar 1999

Firstpage

314

Lastpage

317

Abstract

Experimental data describing circuit and physical design issues that influence the noise immunity of digital latches in mixed-signal smart power circuits are described and discussed. The principal result of this paper is the characterization of the conditions under which substrate noise generated by high power analog circuitry affects digital latches. The experimental data characterize a variety of different noise mitigation techniques for the particular process technology circuit structures, signal/clocking interdependencies, and related conditions

Keywords

MOS integrated circuits; VLSI; flip-flops; integrated circuit layout; integrated circuit noise; interference suppression; mixed analogue-digital integrated circuits; power integrated circuits; HV NMOS process; circuit design issues; digital circuits; digital latches; high power analog circuitry; mixed-signal smart power systems; noise immunity; noise mitigation techniques; physical design issues; substrate noise generation; Circuit noise; Circuit testing; Coupling circuits; Digital circuits; Driver circuits; Integrated circuit noise; Noise generators; Power systems; Registers; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on

Conference_Location

Ypsilanti, MI

ISSN

1066-1395

Print_ISBN

0-7695-0104-4

Type

conf

DOI

10.1109/GLSV.1999.757441

Filename

757441