Analysis of signal and power/ground pin assignment in multi-layer PCB and its impact on signal integrity and crosstalk

In this paper, the impact of signal and power/ground pin assignment in multi-layer printed circuit board (PCB) on signal integrity (SI) performance is studied. Efficient return signal current path plays an important role to preserve SI and minimize unwanted crosstalk. Moreover, a high pin count ratio of signal to power/ground is desirable to increase overall system throughput without trading off SI performance. A case study of a 4-layer organic substrate design is demonstrated for SI and power integrity verification. An optimum pattern of signal and power/ground pins in a regular tile pattern is populated over the floorplan to reduce timing skew (2 times improvement) and suppress crosstalk.