Solutions for logic and processor core design at the 45nm technology node & and below

Author

Royannez, Philippe ; Mair, Hugh ; Clinton, Michael ; Ko, Uming

Author_Institution

Texas Instrum. Inc., Villeneuve-Loubet

fYear

2007

fDate

11-14 Dec. 2007

Firstpage

923

Lastpage

926

Abstract

In this paper we present an overview of techniques and methodologies for processor cores and Digital SoC integration showing how process sensors, circuitry and system control cooperate in order to achieve the best power, performance, area and yield trade-off. We cover combinatorial and sequential logic as well as Memory cores in the context of retention, power gating and adaptive features. Various techniques are also given as example and illustrated by silicon measurements.

Keywords

combinational circuits; logic design; microprocessor chips; sequential circuits; system-on-chip; combinatorial logic; digital SoC integration; logic design; memory cores; process sensors; processor core design; sequential logic; silicon measurements; size 45 nm; yield trade-off; CMOS technology; Control systems; Design for manufacture; Electronic design automation and methodology; Integrated circuit interconnections; Logic design; Manufacturing; Power system interconnection; Process design; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on

Conference_Location

Marrakech

Print_ISBN

978-1-4244-1377-5

Electronic_ISBN

978-1-4244-1378-2

Type

conf

DOI

10.1109/ICECS.2007.4511142

Filename

4511142