• DocumentCode
    3365308
  • Title

    Reconfigurable DSP Architectures for SDR Applications

  • Author

    Muhammad, Najam-ul-Islam ; Khalfallah, Karim ; Knopp, Raymond ; Pacalet, Renaud

  • Author_Institution
    Inst. Eurecom, Sophia-Antipolis
  • fYear
    2007
  • fDate
    11-14 Dec. 2007
  • Firstpage
    971
  • Lastpage
    974
  • Abstract
    Addition of new bands, modes and services in mobile devices means the use of software defined radio (SDR) in the upcoming wireless devices is inevitable. To realize SDR, a common flexible hardware platform is required that supports transmission and reception of the existing radio access technologies. Air-interface and analog/digital conversions make a key part of SDR hardware both on transmitter and receiver. Front end processing block (FEP) of SDR consists of processing blocks required at the air-interface including Time/Frequency conversions, Dot-Products, Energy and Max calculations. We propose a flexible yet efficient hardware design for FEP that will furnish the front-end-functionality requirements of 2G, 3G, 4G, broadcast communication and wireless-LAN standards.
  • Keywords
    digital signal processing chips; radio receivers; radio transmitters; reconfigurable architectures; software radio; air interface; analog-digital conversions; front end processing block; hardware design; radio access technologies; reconfigurable DSP architectures; software defined radio; Application software; Broadcasting; Communication standards; Computer architecture; Digital signal processing; Frequency conversion; Hardware; Radio transmitters; Receivers; Software radio;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
  • Conference_Location
    Marrakech
  • Print_ISBN
    978-1-4244-1377-5
  • Electronic_ISBN
    978-1-4244-1378-2
  • Type

    conf

  • DOI
    10.1109/ICECS.2007.4511154
  • Filename
    4511154