A Methodology to Evaluate the Energy Efficiency of Application Specific Processors

This paper proposes an FPGA based methodology to assess the energy efficiency of application specific processors (ASIPs). This methodology is applied to a video processing algorithm, the motion compensated frame rate conversion (MC-FRC). Previous work has shown that designing a specific instruction set can enhance the performance with a speed-up of more than 80 fold. The purpose of this work is to quantify the energy efficiency of the resulting accelerated processor. This efficiency is evaluated by estimating the power and energy consumption of the processor and of the ASIP when running the algorithm. The results obtained show that the ASIP is more energy efficient than the standard processor by a factor of at least 40. This paper describes the methodology used to compute the power and energy consumption and explains the results through a more detailed analysis of the power and energy consumption.