DocumentCode
3365786
Title
The path and challenges to 90nm radiation hardened technology
Author
Haddad, Nadim ; Chan, Ernesto ; Doyle, Scott ; Kelly, Andrew ; Lawrence, Reed ; Lawson, David ; Patel, Dinu ; Ross, Jason
Author_Institution
Electron. & Integrated Solutions, BAE Syst., Inc., Manassas, VA, USA
fYear
2008
fDate
10-12 Sept. 2008
Firstpage
269
Lastpage
273
Abstract
Preliminary radiation effects analysis on a commercial 90nm CMOS process has been performed to evaluate hardness potential from a process and design perspective, and to identify techniques to promote radiation hardness enhancement towards achieving suitability for low power space applications.
Keywords
CMOS integrated circuits; radiation hardening (electronics); CMOS process; hardness potential; low power space applications; radiation effects analysis; radiation hardened technology; radiation hardness enhancement; size 90 nm; CMOS integrated circuits; CMOS technology; Integrated circuit modeling; Radiation hardening; Random access memory; Single event upset; Transistors; Total ionizing dose; radiation hardening by design; radiation hardening by process; single event effects; single event latch-up;
fLanguage
English
Publisher
ieee
Conference_Titel
Radiation and Its Effects on Components and Systems (RADECS), 2008 European Conference on
Conference_Location
Jyvaskyla
ISSN
0379-6566
Print_ISBN
978-1-4577-0481-9
Type
conf
DOI
10.1109/RADECS.2008.5782725
Filename
5782725
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