A class of single-stage and multi-stage lowpass delta-sigma modulators in 1.2-V 0.13-µm CMOS

Several low-power, single- and multi-stage ΔΣ modulators were designed in a 1.2-V 0.13-nm UMC CMOS process. The distinguishing feature of these modulators is the elimination of operational amplifiers (opamps) in the loop filters and their replacement by comparators with current sources at their outputs. These so-called comparator-based switched-capacitor (CBSC) circuits offer several advantages over opamp-based SC circuits. They consume less power due to their more efficient operation in detecting rather than forcing a virtual ground condition at their input, are more amenable to scaled technology, remove any stability concerns due to their lack of feedback, and can be used in architectures identical or very similar to those available for opamps. The paper reports a discrete-time lowpass first- and second-order single-stage (both simulated) and a third-order multi-stage (measured) single-bit ΔΣ modulator with a signal bandwidth of 62.5 kHz, a sampling frequency of 8 MHz, and an oversampling ratio of 64 with a power consumption of 120 μW, 250 μW, and 360 μW and an SNDR of 57 dB, 71 dB, and 77 dB, respectively.