Title :
Multiple addition of binary serial numbers
Author_Institution :
Ist. di Elettrotec. ed Elettron., Politec. di Milano, Milan, Italy
Abstract :
It is shown how circuits for the addition of several serial binary numbers can be obtained as a combination of parallel counters and memory cells. The various schemes belong to one of three different classes, characterized by the way in which carries, produced by parallel counters, are treated. A comparison is made between the various schemes, in terms of speed and complexity.
Keywords :
digital arithmetic; binary serial numbers; memory cells; multiple addition; parallel counters; Adders; Clocks; Complexity theory; Delay; Memory management; Radiation detectors; Synchronization;
Conference_Titel :
Computer Arithmetic (ARITH), 1978 IEEE 4th Symposium on
Conference_Location :
Santa Monica, CA
DOI :
10.1109/ARITH.1978.6155772
