Design of a High Speed, Low Latency and Low Power Consumption DRAM Using two-transistor Cell Structure

This paper presents a new structure of DRAM, using two-transistor cell. The most important advantages of this structure are: a) High speed read, write and refresh operation b) low data access latency c) low power consumption compared to other structures d) each write/refresh operation can be carried out just in one cycle and e) no need to special process and compatible with standard digital process.