DocumentCode
3366207
Title
How to reduce jitter in fractional PLL
Author
Belfkih, Zakariya ; Bahbouhi, Samir ; Sbaa, Mohamed-Halim ; ELMourabit, Aimad
fYear
2007
fDate
11-14 Dec. 2007
Firstpage
1171
Lastpage
1174
Abstract
the aim of this document is to present the results of the electrical characterization of the PLL, and define all constraints to have a good value of jitter.
Keywords
jitter; phase locked loops; PLL; jitter; phase locked loop; Charge pumps; Clocks; Frequency conversion; Frequency measurement; Gaussian distribution; Jitter; Phase frequency detector; Phase locked loops; Switches; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location
Marrakech
Print_ISBN
978-1-4244-1377-5
Electronic_ISBN
978-1-4244-1378-2
Type
conf
DOI
10.1109/ICECS.2007.4511204
Filename
4511204
Link To Document