Low Power Implementation of Decimation Filters in Multistandard Radio Receiver Using Optimized Multiplication-Accumulation Unit

In this work, the implementation of decimation filters for multistandard wireless transceivers was optimized to reduce its power consumption. The power reduction is achieved through the usage of a MAC unit inside the filters that reduce the total activity and therefore the dynamic power. The multiplication function of the MAC unit is based on the Radix-4 modified-Booth algorithm for the generation of the partial products. For the partial products summation, carry save addition was used. A Pipeline stage is then introduced to allow the accumulation of the result of the partial product summation step and the previous multiplications results. The power consumption of the different filters in the multistandard radio receiver was already optimized using the clock-gating technique at the circuit level. Experimental results show a power reduction of 9,48% when using the optimized MAC unit in comparison to the same architecture of the filters where only clock-gating technique is used and a total reduction of 61,98% compared to the implementation without any optimization.