Finite state machine partitioning for I/O-limited design

Author

Kuo, Ming-Ter ; Liu, Lung-Tien ; Cheng, Chung-Kuan

Author_Institution

Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA

fYear

1995

fDate

31 May-2 Jun 1995

Firstpage

68

Lastpage

72

Abstract

We proposed a Finite State Machine (FSM) partitioning procedure for minimizing the number of inputs/outputs of FSMs. The FSM partition is obtained by partitioning the set of transitions that describe the behavior of an FSM. An extended FM-based graph partitioning algorithm is applied for transition partitioning. We also devise a state information minimization technique to further reduce the number of interconnections between the FSMs required for communication. Experimental results for MCNC benchmarks show that our algorithm has favorable results over circuit partitioning algorithms on the netlist level

Keywords

finite state machines; graph theory; logic CAD; logic partitioning; minimisation of switching nets; FSM partitioning procedure; I/O-limited design; finite state machine; graph partitioning algorithm; interconnections reduction; sequential logic synthesis; state information minimization; transition partitioning; Automata; Benchmark testing; Circuit synthesis; Circuit testing; Clocks; Logic devices; Minimization; Partitioning algorithms; Pins; Programmable logic devices;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-2773-X

Type

conf

DOI

10.1109/VTSA.1995.524636

Filename

524636