Efficient and Accurate Models of Output Transition Time in CMOS Logic

In automated design of Very Large Scale of Integration (VLSI) digital circuits with a standard cell approach, accurate timing analysis is of utmost importance. Due to the strong impact of the input (rise/fall) transition time on the delay of succeeding gates in nanometer technologies, the output transition time of CMOS gates must be modeled with adequate accuracy [1]. In this paper, a simple and an accurate output transition time model based on the approach in [2]-[5] are proposed. Extensive model validation has been made by means of Spectre simulations on a 90 nm technology, which confirm the good accuracy of the models.