DocumentCode :
3366717
Title :
Optimized sample planning for wafer defect inspection
Author :
Williams, Ross ; Gudmundsson, D. ; Monahan, K. ; Shanthikumar, J.
Author_Institution :
Intel Corp., Rio Rancho, NM
fYear :
1999
fDate :
1999
Firstpage :
43
Lastpage :
46
Abstract :
Increasing fab construction costs, shortening product life cycles, and eroding market prices have become critical realities for today´s semiconductor manufacturers. Consequently, many semiconductor facilities are now facing increasing pressure to quickly reach and maintain profitability by achieving faster yield ramps and sustaining higher product yields, while concurrently keeping the operational costs to a minimum. Inherently, these goals are in constant conflict, and the problem of optimally allocating various types of defect inspection equipment in an advanced semiconductor manufacturing line can be complex. The optimal sampling requirements are also dynamic, and are dependent upon the process technology, the product operational phase, and the business environment
Keywords :
inspection; integrated circuit manufacture; manufacturing resources planning; defect inspection equipment allocation; optimized sample planning; sampling plan dynamics; semiconductor facilities; semiconductor manufacturing line; wafer defect inspection; yield ramps; Capacity planning; Costs; Inspection; Manufacturing processes; Monitoring; Process control; Production; Sampling methods; Semiconductor process modeling; Virtual manufacturing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Manufacturing Conference Proceedings, 1999 IEEE International Symposium on
Conference_Location :
Santa Clara, CA
ISSN :
1523-553X
Print_ISBN :
0-7803-5403-6
Type :
conf
DOI :
10.1109/ISSM.1999.808734
Filename :
808734
Link To Document :
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