Process Variation Aware Comprehensive Layout Synthesis for Yield Enhancement in Nano-meter CMOS

This paper proposes a process variation aware cell layout synthesis for standard cell yield enhancement considering lithographic process variation. We evaluated the catastorphic defects of intra-cell routing in defocus and exposure dose conditions, modeled a fault probability in overall process window and select the optimum layout in comprehensively generated layouts of a logic cells. Experimental results demonstrated that the best case layout showed 15 times improvement over the worst case layout in terms of the fault probability. assuming defocus and exposure dose distribute within 100nm and 5% for 65nm CMOS process.