High Speed, Low Power Four-Quadrant CMOS Current-Mode Multiplier

Author

Naderi, A. ; Khoei, A. ; Hadidi, Kh

Author_Institution

Urmia Univ., Urmia

fYear

2007

fDate

11-14 Dec. 2007

Firstpage

1308

Lastpage

1311

Abstract

In this paper a new CMOS current-mode four-quadrant analog multiplier and divider circuit based on squarer circuit is proposed. The dual translinear loops is the basic building block in realization scheme. Supply voltage is 3.3V. The major advantages of this multiplier are high speed, low power, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35Â¿m standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 1.1%, a THD of 0.97% in 1MHz, a -3dB bandwidth of 41.8MHz and a maximum power consumption of 0.34mW.

Keywords

CMOS analogue integrated circuits; analogue multipliers; dividing circuits; CMOS current-mode multiplier; THD; bandwidth 41.8 MHz; dc offset error; divider circuit; dual translinear loops; four-quadrant analog multiplier; high speed multiplier; low power four-quadrant multiplier; realization scheme; size 0.35 mum; squarer circuit; Bandwidth; CMOS analog integrated circuits; CMOS technology; Circuit simulation; Energy consumption; Laboratories; Linearity; MOSFETs; Microelectronics; Voltage; CMOS analog multiplier; current mode; four quadrant; squarer circuit; translinear loop;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on

Conference_Location

Marrakech

Print_ISBN

978-1-4244-1377-5

Electronic_ISBN

978-1-4244-1378-2

Type

conf

DOI

10.1109/ICECS.2007.4511238

Filename

4511238