Timing and power simulation for deep sub-micron ICs

Due to the performance limitations of electrical-level circuit simulators like SPICE, gate- and transistor-level timing and power simulation tools are becoming increasingly important to the IC design community. Industry trends in circuit density, operating speed, and power supply voltage demand higher and higher levels of modeling sophistication to reliably and accurately predict circuit functionality and performance. This paper compares and contrasts the latest modeling and timing simulation strategies from the point-of-view of accuracy and efficiency. We assess the usefulness of various simulation techniques with respect to their ability to accommodate important second-order phenomena like short and narrow channel effects, charge sharing, sub-threshold conduction, etc. These effects can impose serious limitations on the usefulness of design tools for increasingly common submicron fabrication technologies. ADM, a transistor-level simulation strategy based on efficient analytic solution of partitioned channel-connected components, is shown to address these concerns directly and automatically. An industry benchmark summary of an assortment of microprocessor, memory, and communication designs is presented to demonstrate the viability of this method