DocumentCode
3366971
Title
Layer yield estimation based on critical area and electrical defect monitor data
Author
Milor, Linda ; Hill, Gene ; Peng, Yeng
Author_Institution
AMD, Sunnyvale, CA, USA
fYear
1999
fDate
1999
Firstpage
99
Lastpage
102
Abstract
It is often desirable to forecast the random yield of each layer of new products. In this work we provide a yield forecasting methodology based on critical area, which goes beyond comparing die areas of products and accounts for layout density. This methodology forecasts the random yield loss per metal or poly layers by comparing the critical area of single layer defect monitors (DMs) to that of the product. In this paper, we discuss the design of DMs and sources of inaccuracy in product yield estimation based on DM data. In addition, we show how DMs can be useful in forecasting how the sizing of metal, poly, and local interconnect layers impacts random layer yield
Keywords
estimation theory; integrated circuit yield; monitoring; critical area; electrical defect monitor data; layer yield estimation; layout density; local interconnect layers; metal layers; polysilicon layers; random layer yield; random yield loss per layer; single layer defect monitors; yield forecasting methodology; Delta modulation; Digital TV; Distributed decision making; Load forecasting; Monitoring; Testing; Uncertainty; Yield estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing Conference Proceedings, 1999 IEEE International Symposium on
Conference_Location
Santa Clara, CA
ISSN
1523-553X
Print_ISBN
0-7803-5403-6
Type
conf
DOI
10.1109/ISSM.1999.808747
Filename
808747
Link To Document