PLABEK: a complete automatic test pattern generation system for break faults in programmable logic arrays

Author

Hwang, Gwo-Haur ; Shen, Wen-Zen ; Tenqchen, Shing

Author_Institution

VLSI Support Center, MOTC, Taoyuan, Taiwan

fYear

1995

fDate

31 May-2 Jun 1995

Firstpage

87

Lastpage

92

Abstract

In this paper, a complete PLA break fault ATPG system, PLABEK, is proposed. PLABEK contains four main parts: 1) break fault collapsing; 2) pruning algorithm based test pair generation; 3) serial-fault-injection parallel-bit-operation event-driven break fault simulation; and 4) testability-measure-based fault ordering. Experimental results show that PLABEK can generate complete compact test sequences for PLA´s break faults very fast

Keywords

automatic test software; circuit analysis computing; fault diagnosis; integrated circuit testing; logic testing; programmable logic arrays; ATPG system; PLA faults; PLABEK; automatic test pattern generation system; break faults; compact test sequences; event-driven break fault simulation; fault collapsing; parallel-bit-operation; programmable logic arrays; pruning algorithm; serial-fault-injection; test pair generation; testability-measure-based fault ordering; Automatic logic units; Automatic test pattern generation; Circuit faults; Circuit testing; Fault detection; Logic testing; Programmable logic arrays; Programmable logic devices; Semiconductor device modeling; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-2773-X

Type

conf

DOI

10.1109/VTSA.1995.524639

Filename

524639