Title :
PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications
Author :
Siwiec, Krzysztof ; Borejko, Tomasz ; Pleskacz, Witold A.
Author_Institution :
Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Warsaw, Poland
Abstract :
In this paper low-voltage LC voltage-controlled oscillator (VCO) with low sensitivity to process, voltage and temperature (PVT) variations has been presented. VCO operates at 3.2 GHz and its output signal frequency is divided by 2 in quadrature divider to generate quadrature signals at 1.6 GHz. The NMOS cross-coupled architecture, proper varactor biasing, tuning curve linearization technique and switched-capacitor (SC) current source were used to reduce the sensitivity to PVT variations. The LC-VCO was designed with the usage of Low-Leakage UMC 90 nm CMOS technology. It achieves phase noise of -117 dBc/Hz at 1 MHz offset and draws 1.2 mA (VCO+Quadrature Divider) from 1.2 V supply voltage.
Keywords :
CMOS integrated circuits; Global Positioning System; linearisation techniques; switched capacitor networks; varactors; voltage dividers; voltage-controlled oscillators; CMOS technology; GPS/Galileo applications; NMOS cross-coupled architecture; PVT tolerant LC-VCO; PVT variations; SC current source; VCO+quadrature divider; current 1.2 mA; frequency 1 MHz; frequency 1.6 GHz; frequency 3.2 GHz; low-voltage LC voltage-controlled oscillator; output signal frequency; proper varactor biasing; quadrature signals; size 90 nm; switched-capacitor current source; tuning curve linearization technique; voltage 1.2 V; Phase locked loops; Phase noise; Power demand; Tuning; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on
Conference_Location :
Cottbus
Print_ISBN :
978-1-4244-9755-3
DOI :
10.1109/DDECS.2011.5783042