Title :
Application of defect inspection in development of 0.25 and 0.18 micron technology
Author :
Guldi, R. ; Winter, T. ; PapaRao, S. ; Smith, J. ; Sridhar, N. ; Garvin, J. ; Metteer, B.
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
We present a general strategy for identifying systematic and random defect issues during the initial stages of development of 0.25 μm and 0.18 μm logic technology. This strategy includes Critical Area Analysis modeling, improved defect monitoring techniques, methodology for prioritizing tools for continuous improvement to reduce random particles, and the use of back-end-of-line monitors. Technology development requires stringent attention to systematic defects, which dominate early yield learning. For all defect issues, we discuss practical aspects of inspection tool recipe sensitization which optimize the capture rate of visual yield limiters, enabling fast feedback problem resolution and high confidence matching of electrical faults and physical defects
Keywords :
fault diagnosis; inspection; integrated circuit modelling; integrated circuit yield; integrated logic circuits; process monitoring; 0.18 μm logic technology; 0.18 mum; 0.25 μm logic technology; 0.25 mum; back-end-of-line monitors; capture rate; critical area analysis modeling; defect inspection; defect monitoring techniques; early yield learning; electrical faults; fast feedback problem resolution; high confidence matching; inspection tool recipe sensitization; physical defects; random defect issues; random particle reduction; systematic defect issues; visual yield limiters; Circuit faults; Computer aided analysis; Continuous improvement; Control systems; Inspection; Instruments; Integrated circuit technology; Integrated circuit yield; Logic devices;
Conference_Titel :
Semiconductor Manufacturing Conference Proceedings, 1999 IEEE International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-5403-6
DOI :
10.1109/ISSM.1999.808756
