A 16 bit low voltage low power Delta Sigma modulator

A low-voltage and low-power Delta Sigma modulator is presented in this paper. The modulator employs a third-order single-loop topology with feed-forward path and a single-bit quantizer. The summing circuit becomes simpler in single-bit modulator, which avoids an extra amplifier and decreases power dissipation by getting rid of the traditional switch-capacitor-amplifier style in multi-bit output structure. By utilizing the advanced switched-capacitor(SC) integrator topology especially designed for the technology of zeros optimization, the huge difference between capacitors due to the small zero feedback coefficient is improved, which can save the chip area efficiently. The modulator, designed in SMIC 0.18-μm CMOS process, achieves a 93 dB signal to noise ratio (SNR) in a 1 KHz signal bandwidth and consumes 1.35 mW from a 1.5 V supply.