Configurable VLSI architecture of a 3-input floating-point adder

In this paper, we present the design and the implementation of an IEEE 754-compliant floating-point adder with three inputs. The design is based on a 4-level pipeline stage in order to distribute the critical paths and to maximize the performance. We examine the data dependencies to minimize the number of the pipeline stages. The design is customizable to support various floating-point formats, including the standard single precision and double precision formats. The proposed design with the single precision, 32-bit floating-point format consumes 98712 mum square area and has an operating speed of 556 MHz in a 0.18-mum process.