A Fractional Frequency Synthesizer Using Frequency Locked Loop

This paper presents a new architecture for wideband fractional frequency synthesizer. The architecture is based on frequency locked loop (FLL). Fractional division is implemented in this FLL by using two feedback loops which are having different frequency division ratio N and N+1. The error signals generated by these two loops are mixed together with different gains alpha and beta, in analog means, and then it is given to a voltage controlled oscillator (VCO). The integer part of the division ratio is controlled by N and the fractional part is controlled by the relative values of alpha and beta. The architecture is verified at circuit level using SPECTRE RF circuit simulator in a 0.18 mum CMOS technology. In the implementation example, input reference frequency is 50 MHz, frequency division factor is 8.25 and loop bandwidth is 1.6 MHz.