Building Ultra-Low-Power Low-Frequency Digital Circuits with High-Speed Devices

Leakage current is the main source of power dissipation in low-frequency digital circuits implemented in deep submicron processes. This contribution introduces a novel active-mode leakage reduction technique for Ultra-Low-Power (ULP) low-frequency applications. It is based on the ULP CMOS logic style achieving negative-VGS self-biasing. ULP logic gates have static current reduced by several orders of magnitude. For a commercial 0.13-¿m technology, power consumption of ULP gates at low frequencies is lower than standard CMOS counterparts even considering high-VT devices, subthreshold operation and reverse body biasing. ULP gates are shown to be very stable against process, voltage and temperature variations.