DocumentCode
3367298
Title
LUT-Based Power Macromodeling Technique for DSP Architectures
Author
Durrani, Yaseer A. ; Riesgo, Teresa
Author_Institution
Univ. Polytech. de Madrid, Madrid
fYear
2007
fDate
11-14 Dec. 2007
Firstpage
1416
Lastpage
1419
Abstract
In this paper, we present a look-up-table (LUT) based power macromodeling technique for digital signal processing (DSP) architecture in terms of the statistical knowledge of their primary inputs. During the power estimation procedure, the sequence of an input stream is generated by a genetic algorithm using input metrics. Then, a Monte Carlo zero-delay simulation is performed and a power dissipation macromodel function is built from power dissipation results. From then on, this macromodel function can be used to estimate power dissipation of the system just by using the statistics of the macro-block´s primary inputs. In experiments with the DSP system, the average error is 31.23%.
Keywords
FIR filters; Monte Carlo methods; estimation theory; genetic algorithms; signal processing; table lookup; Monte Carlo zero-delay simulation; digital signal processing architecture; finite impulse response filter; genetic algorithm; look-up-table; power dissipation macromodel function; power estimation; statistical knowledge; Circuit simulation; Digital signal processing; Electronic design automation and methodology; Finite impulse response filter; Genetic algorithms; Power dissipation; Power generation; Statistics; Table lookup; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location
Marrakech
Print_ISBN
978-1-4244-1377-5
Electronic_ISBN
978-1-4244-1378-2
Type
conf
DOI
10.1109/ICECS.2007.4511265
Filename
4511265
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