Title :
SAT-based analysis of sensitisable paths
Author :
Sauer, Matthias ; Czutro, Alexander ; Schubert, Tobias ; Hillebrecht, Stefan ; Polian, Ilia ; Becker, Bernd
Author_Institution :
Albert-Ludwigs-Univ. Freiburg, Freiburg, Germany
Abstract :
Manufacturing defects in nanoscale technologies have highly complex timing behaviour that is also affected by process variations. While conventional wisdom suggests that it is optimal to detect a delay defect through the longest sensitisable path, non-trivial defect behaviour along with modelling inaccuracies necessitate consideration of paths of well-controlled length during test generation. We present a generic methodology that yields tests through all sensitisable paths of user-specified length. The resulting tests can be employed within the framework of adaptive testing. The methodology is based on encoding the problem as a Boolean-satisfiability (SAT) instance and thereby leverages recent advances in SAT-solving technology.
Keywords :
Boolean functions; automatic test pattern generation; computability; fault diagnosis; logic testing; nanotechnology; Boolean-satisfiability instance; SAT instance; SAT-based analysis; SAT-solving technology; adaptive testing; conventional wisdom; delay defect; generic methodology; manufacturing defects; modelling inaccuracy; nanoscale technology; nontrivial defect behaviour; process variations; sensitisable paths; test generation; timing behaviour; user-specified length; well-controlled length; Circuit faults; Delay; Digital TV; Encoding; Logic gates; Optimization; Programmable logic arrays;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on
Conference_Location :
Cottbus
Print_ISBN :
978-1-4244-9755-3
DOI :
10.1109/DDECS.2011.5783055