DocumentCode :
3367480
Title :
Influence of parasitic memory effect on single-cell faults in SRAMs
Author :
Irobi, Sandra ; AL-Ars, Zaid ; Hamdioui, Said ; Renovell, Michel
Author_Institution :
CE Lab., Delft Univ. of Technol., Delft, Netherlands
fYear :
2011
fDate :
13-15 April 2011
Firstpage :
159
Lastpage :
162
Abstract :
Parasitic node capacitance and faulty node voltage of a defective node can induce serious parasitic effects on the electrical behavior of SRAMs. This paper evaluates the impact of parasitic memory effect on the detection of single-cell faults in SRAMs. It demonstrates that detection is significantly influenced by parasitic node components; something that is often not accounted for during memory testing. Finally, it shows the impact of parasitic node components on all possible opens in the SRAM memory cell array, using node voltages from GND to VDD.
Keywords :
SRAM chips; capacitance; fault diagnosis; logic testing; SRAM; defective node; faulty node voltage; memory testing; parasitic memory effect; parasitic node capacitance; single cell fault; Arrays; Circuit faults; Logic gates; Metals; Parasitic capacitance; Random access memory; Parasitic memory effect; SRAMs; static faults;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on
Conference_Location :
Cottbus
Print_ISBN :
978-1-4244-9755-3
Type :
conf
DOI :
10.1109/DDECS.2011.5783071
Filename :
5783071
Link To Document :
بازگشت