Title :
Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations
Author :
Iwagaki, Tsuyoshi ; Saluja, Kewal K.
Author_Institution :
Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol. (JAIST), Ishikawa, Japan
Abstract :
Hold-time violations in a scan circuit may occur both in the scan chain and in its combinational logic part. If a hold-time violation occurs on the scan path from one scan cell to another, it is also likely to happen on short functional paths between the two cells, which have clock skew. This paper is intended to indirectly detect hold-time violations on short functional paths using scan shift operations. A greedy approach to scan chain ordering is presented to detect as many hold-time violations as possible using scan shift operations. Extensive experiments are conducted to detect hold-time violations on short functional paths of various lengths by scan shift operations. Experimental results show that many hold-time violations on short functional paths can be detected by choosing an appropriate order of the scan cells in the scan chain.
Keywords :
combinational circuits; logic testing; clock skew induced hold-time violation; combinational logic part; functional path; scan chain ordering; scan circuit; scan shift operation; Benchmark testing; Circuit faults; Clocks; Delay; Layout; Very large scale integration;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on
Conference_Location :
Cottbus
Print_ISBN :
978-1-4244-9755-3
DOI :
10.1109/DDECS.2011.5783075