Power consumption traces realignment to improve differential power analysis

Cryptographic devices can be subject to side-channel attacks. Among those attacks, Differential Power Analysis (DPA) has proven to be very effective and easy to perform. Several countermeasures have been proposed in the literature. However, the effectiveness of these counter measures is still evaluated by resort-ing to intensive DPA simulations and constitutes a very time-consuming design task. In this paper we show that the knowledge of the structure of the circuit can be exploited to improve performances of the DPA. We propose to realign power consumption traces according timing information (i.e., path delays). We show the usefulness of the proposed method by comparing the efficiency of classic DPA w.r.t. timing aware DPA.