A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms

In this paper, a cost-effective and power-aware IP core design for computing the MPEG4 SA-DCT/IDCT is proposed. The proposed IP core has been developed based on the concept of programmable processors to provide flexibility in dynamically configuring the hardware. The techniques exploited include adder-based distributed arithmetic, common subexpression sharing, canonical signed digit (CSD) representation, and equipping interleaved RAM. The proposed IP core also possesses the feature of power-aware design flexibility allowing the trade-off of lower power consumption with less demand of data precision in developing its instruction library. This design has been realized based on a 0.35-μm CMOS technology and costs about 3100 gates with 32 words of RAM, which can achieve real-time processing of the texture coding in MPEG4 SP@L3 and ACE@L2 codec systems for the CIF video at 30 frames per second (fps).