Title :
Characterization of digital cells for statistical test
Author :
Hopsch, Fabian ; Lindig, Michael ; Straube, Bernd ; Vermeiren, Wolfgang
Author_Institution :
Fraunhofer IIS/EAS, Dresden, Germany
Abstract :
Integrated circuits necessitate high quality and high yield. Defects and parameter variations are a main issue affecting both aspects. In this paper a method for characterization for statistical test is presented. The characterization is carried out for a set of digital cells using Monte Carlo fault simulation at electrical level. The results show that only a small amount of faults are being manifested as stuck-at faults. Many faults lead to a mix of different behaviours for various test sequences and parameter configurations. For a digital cell, the necessary test sequences for detecting all detectable faults are derived from the simulation results. Since the effort for the characterization is high, first investigations to reduce this effort are presented.
Keywords :
Monte Carlo methods; fault simulation; integrated circuit testing; integrated circuit yield; logic testing; Monte Carlo fault simulation; digital cell characterization; electrical level; integrated circuit quality; integrated circuit yield; parameter variation; statistical test; stuck-at faults; Circuit faults; Delay; Frequency division multiplexing; Integrated circuit modeling; Load modeling; Logic gates; Monte Carlo methods; Monte Carlo fault simulation; characterization; defect-oriented test; parameter variation; statistical test;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on
Conference_Location :
Cottbus
Print_ISBN :
978-1-4244-9755-3
DOI :
10.1109/DDECS.2011.5783089
