Characterization of digital cells for statistical test

Integrated circuits necessitate high quality and high yield. Defects and parameter variations are a main issue affecting both aspects. In this paper a method for characterization for statistical test is presented. The characterization is carried out for a set of digital cells using Monte Carlo fault simulation at electrical level. The results show that only a small amount of faults are being manifested as stuck-at faults. Many faults lead to a mix of different behaviours for various test sequences and parameter configurations. For a digital cell, the necessary test sequences for detecting all detectable faults are derived from the simulation results. Since the effort for the characterization is high, first investigations to reduce this effort are presented.