Standards for System Level Design

Standards are emerging in the System Level Design area. After an initial period where models were created by a reduced number of experts, the trend is now to integrate models coming from various sources. In order to reduce integration effort when creating virtual prototypes, standards have been defined to increase model to model, and model to tool interoperability. After presenting the rationale for defining standards, and introducing the languages used in the field, we give a status of the currently available standards for System on Chip modeling and virtual prototype integration. We also identify the next steps, and indicate the next topics to be standardized, from a user perspective.