Differential Edge-Triggered Flip-Flops Using Neuron-MOS Transistors

Novel differential flip-flops using neuron-MOS transistors are presented, including single edge-triggered flipflop and double edge-triggered flip-flop. In the new differential flip-flops, a pair of n-channel multiple-input neuron-MOS pull down logic networks is used to replace the nMOS logic tree in the conventional differential flip-flops. The construction of the circuits has been simplified by employing the multiple-input neuron-MOS transistors. HSPICE simulations using TSMC 0.35μm 2-ploy 4-metal CMOS technology have verified the effectiveness of the proposed design scheme. The simulated results of propagation delay and power dissipation are also given.