• DocumentCode
    3368009
  • Title

    High-performance hardware accelerators for sorting and managing priorities

  • Author

    Sklyarov, Valery ; Skliarova, Iouliia ; Mihhailov, Dmitri ; Sudnitson, Alexander

  • Author_Institution
    DETI/IEETA, Univ. of Aveiro, Aveiro, Portugal
  • fYear
    2011
  • fDate
    13-15 April 2011
  • Firstpage
    313
  • Lastpage
    318
  • Abstract
    The paper describes the hardware implementation and optimization of algorithms that process tree-like data structures which are needed for numerous practical applications in such areas as databases, embedded systems, and networks requiring priority management. The emphasis is done on applications that involve fast processing of new incoming data items, such as resorting. Parallelism is achieved by constructing N binary trees (N>;1) and applying concurrent operations to N trees at the same time with the aid of N communicating processing modules. It is shown that the considered technique can efficiently be combined with sorting networks, which gives new potentialities for optimization. Modeling in software, experiments with FPGA-based circuits on different computing platforms, and comparisons with the other known methods demonstrate that the performance is increased significantly. It is also shown that the proposed algorithms are easily scalable.
  • Keywords
    concurrency control; field programmable gate arrays; parallel algorithms; sorting; tree data structures; FPGA-based circuit; algorithm optimization; binary tree; concurrent operation; database; embedded system; high-performance hardware accelerator; parallel algorithm; priority management; priority sorting; sorting network; tree-like data structure; Adaptation model; Computational modeling; Field programmable gate arrays; Graphics processing unit; Hardware; Integrated circuit modeling; US Department of Defense; fast resorting; hierarchical FSMs; managing priorities; parallelization; sorting networks; tree-like data structures;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on
  • Conference_Location
    Cottbus
  • Print_ISBN
    978-1-4244-9755-3
  • Type

    conf

  • DOI
    10.1109/DDECS.2011.5783103
  • Filename
    5783103